The present disclosure relates to reference voltage supply circuits, and more particularly to reference voltage supply circuits utilizing a work function difference.
In recent years, with development in the mobile market and the low power consumption market, microcomputers capable of standby with low power consumption have been demanded. In most cases, only a reference voltage supply circuit operates in a standby mode of a microcomputer, and thus lower power consumption of the reference voltage supply circuit is demanded.
Reference voltage supply circuits are largely divided into three types, a bandgap reference type, a MOS-Vth difference type, and a work function difference type. Out of the types, the work function difference type has excellent characteristics of low power consumption, and low dependency on process variations of a reference voltage value. However, this type has the problem of high temperature dependency, and is therefore generally not utilized.
A conventional reference voltage supply circuit utilizing a work function difference will be described below with reference to the drawings. (See, for example, Japanese Patent Publication No. S60-150115.)
The configuration of a conventional reference voltage supply circuit utilizing a work function difference will be described with reference to FIG. 9. As shown in FIG. 9, the conventional reference voltage supply circuit includes a p-channel metal oxide semiconductor (PMOS) transistor having a source to which a power supply voltage Vdd is applied, an NG_NMOS coupled in series to the PMOS, and a PG_NMOS coupled in series to the NG_NMOS.
The NG_NOMOS is a conventional n-channel metal oxide semiconductor (NMOS) transistor having an n+-type gate electrode doped with phosphorus (P), and a threshold voltage of about 0.6 V. Different from a conventional NMOS, the PG_NMOS has a p+-type gate electrode doped with boron (B). The p+-type gate electrode has a higher work function than the n+-type gate electrode by about 1.0 V. As a result, the PG_NMOS has a threshold voltage of about 1.6 V.
The PMOS functions as a constant current supply, and has a gate to which Vg_p1 is input. The PMOS may be a resistor. The gates of the NG_NMOS and the PG_NMOS are directly coupled to the drain of the PMOS. The potential of the gates is defined as Vg_n1. Furthermore, the NG_NMOS is located in a shallow p-type well of a deep n-type well. Since the p-type well is coupled to the source of the NG_NMOS, the potential of the p-type well is not fixed to Gnd, and eventually becomes a reference voltage Vref.
The NG_NMOS and the PG_NMOS have the same gate width W and the same gate length.
The three transistors of the circuit are coupled in series, and thus equal source/drain currents Ids constantly flow through the transistors.
In general, Ids in a saturated state of a MOS transistor is expressed by the following equation.Ids=β/2×(Vgs−Vth)2 Where Ids of the NG_NMOS is Idsng, the threshold voltage is Vtng, the source voltage is Vsng, Ids of the PG_NMOS is Idspg, the threshold voltage is Vtpg, the source voltage is Vspg=0 V, and the work function difference between the p+-type gate electrode and the n+-type gate electrode is Φpn, the following equations are obtained.Idsng=β/2×(Vg—n1−Vsng−Vtng)2 Idspg=β/2×(Vg—n1−Vspg−Vtpg)2=β/2×(Vg—n1−Vtng−Φpn)2 From the equations and the equation Idsng=Idspg,Vg—n1−Vsng−Vtng=Vg—n1−Vtng−Φpn, and Vref=Vsng=Φpn are obtained, and the source voltage Vsng of the NG_NMOS is equal to Φpn. That is, the work function difference Φpn between the p+-type gate electrode and the n+-type gate electrode can be extracted using the source voltage Vsng of the NG_NMOS as a reference voltage Vref.
FIG. 10 illustrates the operating point of reference voltage generation. In FIG. 10, the horizontal axis represents the gate voltage Vg_n1, and the vertical axis represents Log(Ids). The curves A-D respectively show the Ids characteristics of the NG_NMOS at a room temperature, the Ids characteristics of NG_NMOS at a temperature of 150° C., the Ids characteristics of the PG_NMOS at the room temperature, the Ids characteristics of the PG_NMOS at the temperature of 150° C. The intersections between a reference current flowing from the PMOS and the Ids characteristics determine the reference voltage Vref.
As described above, the following equations are obtained.Idsng=β/2×(Vg—n1−Vsng−Vtng)2 Idspg=β/2×(Vg—n1−Vtng−Φpn)2 The terms indicate the temperature characteristics, and only the term Φpn (=Vsng) is different. That is, only the temperature characteristics of Φpn appears in Vsng, which is the reference voltage Vref. There is no influence of the temperature dependency of the reference current in the theoretical formulas.
FIG. 11 illustrates the temperature characteristics of the reference voltage Vref which are represented by measured values. As clear from the graph, the reference voltage Vref has negative temperature characteristics (i.e., about −0.6 mV/K), which are generally difficult to use as a reference voltage. In order to improve the temperature characteristics, various suggestions have been made (see, e.g., Japanese Patent Publication No. 2008-66649 and Japanese Patent Publication No. 2008-263195), but none of them are effective.
Japanese Patent Publication No. 2008-66649 teaches using an NG_NMOS transistor and a PG_NMOS transistor with different gate lengths to generate a reference voltage at a point at which Vt has low temperature dependency. However, the problem is that the point of the low temperature dependency shifts due to process variations.
Japanese Patent Publication No. 2008-263195 aims to cancel temperature characteristics using the work function difference (with positive temperature characteristics) between an n+-type gate electrode and an n−-type gate electrode (with low concentration impurities) and the work function difference (with negative temperature characteristics) between the n+-type gate electrode and a p+-type gate electrode. However, the problems is that the positive and negative temperature characteristics have different slopes, in particular, the work function difference between the n+-type gate electrode and the n−-type gate electrode have great process variations.